(1) Field of the Invention
The present invention relates to a solid-state imaging device including plural pixel cells arranged in a matrix, and a column signal lines connected to plural amplifying transistors corresponding to a column of the associated plural pixel cells.
(2) Description of the Related Arts
Recently, manufacturers are promoting developments of MOS solid-state image sensors as solid-state imaging devices applicable to video cameras and electronic still cameras. These solid-state imaging devices are structured to amplify, using a MOS transistor, a signal obtained by a photoelectric conversion unit on a cell basis, and pick up the amplified signal.
FIG. 8 is a circuit diagram illustrating a unit pixel included in a conventional solid-state imaging device having a MOS transistor and a circuit surrounding the unit pixel.
A unit pixel 103 included in a MOS image sensor has a photodiode (PD) 132, a transfer transistor 134, a floating diffusion (FD) 138, a reset transistor 136, and an amplifying transistor 142.
The photodiode (PD) 132 photoelectrically converts incident light to generate a charge.
Next, when the transfer transistor 134 turns on, the charge generated by the photodiode (PD) 132 is transferred to the floating diffusion (FD) 138.
Described herewith is an externally-reading operation from the unit pixel 103 via a column signal line 153. First, the floating diffusion (FD) 138 is reset at a high level of voltage. Then, a photocharge detected by the photodiode (PD) 132 is transferred to the floating diffusion (FD) 138. The level of voltage of the floating diffusion (FD) 138 varies depending on the charge amount. Next, the amplifying transistor 142 forwards to the column signal line 153 the change in the level of voltage of the floating diffusion (FD) 138 as a pixel signal.
The following shall provide a brief description of an operation of a circuit in the conventional solid-state imaging device with reference to a timing diagram and a potential diagram of the conventional solid-state imaging device.
FIGS. 9A and 9B are timing diagrams showing the operation of the conventional solid-state imaging device. The drawings show timings of a drain driving pulse VDDCELL applied to a drain line 157, a reset signal RST applied to a reset line 156, a transfer gate pulse TRANS applied to a transfer gate line 155, the floating diffusion (FD) 138, and the column signal line 153.
Here, FIG. 9A is a timing diagram showing the operation of the conventional solid-state imaging device with no electric charge applied on the photodiode (PD) 132. Meanwhile, FIG. 9B is a timing diagram showing the operation of the conventional solid-state imaging device with an electric charge applied to the photodiode (PD) 132.
In FIGS. 9A and 9B, first, the drain driving pulse VDDCELL (high level) is applied to the drain line 157, so that the drain line 157 is brought to a VDD level (high level). Next, when the reset signal RST (high level) is applied to the reset line 156 to rise (t1), the reset transistor 136 turns on, and the floating diffusion (FD) 138 is brought high (t1 to t2, FD reset level of voltage 1).
Then, the reset signal RST falls (t2).
A voltage of the column signal line 153 (reset level) is provided to a circuit, in a next stage, connected at the column signal line 153, the voltage which has decreased from a voltage of the floating diffusion (FD) 138 (FD reset level of voltage 1) by a drain-gate voltage (Vth) of the amplifying transistor 142.
Then, the transfer gate pulse TRANS (high level) is applied to the transfer gate line 155 (t3 to t4). Here, when no incident light is transferred into the photodiode (PD) 132, and thus no signal charge (photoelectron) is accumulated in the photodiode (PD) 132, the level of voltage of the floating diffusion (FD) 138 remains to be the FD reset level of voltage 1, and is unchanged (t3 to t5 in FIG. 9A) even though the transfer transistor 134 turns on.
Meanwhile, when incident light is transferred into the photodiode (PD) 132, and thus a signal charge (photoelectron) is accumulated in the photodiode (PD) 132, the signal charge (photoelectron) is transferred from the photodiode (PD) 132 to the floating diffusion (FD) 138, and then the level of voltage of the floating diffusion (FD) 138 goes low depending on the signal charge (photoelectron). The voltage of the column signal line 153 lowered by the drain-gate voltage (Vth) of the amplifying transistor 142 goes low (t3 to t5 in FIG. 9B), following the lowered level of voltage of the floating diffusion (FD) 138. The potential (signal level) of the column signal line 153 is provided again to the circuit in the next stage.
Then, setting the drain driving pulse VDDCELL to a low level and applying the reset signal RST to the reset transistor 136 (t5 to t6) is brings the floating diffusion (FD) 138 to a low level (from t5 downward). The circuit in the next stage detects the difference between the reset level and the signal level, and forwards the difference as a pixel signal.
Described next are potentials of the photodiode (PD) 132 and the floating diffusion (FD) 138 when the incident light is transferred into the photodiode (PD) 132, and then the signal charge (photoelectron) is accumulated in the photodiode (PD) 132.
FIG. 10 shows potentials of the photodiode (PD) 132 and the floating diffusion (FD) 138 in the conventional solid-state imaging device. The horizontal direction indicates locations of the photodiode (PD) 132 and the floating diffusion (FD) 138, and the vertical direction indicates potentials (high as indicated bottom).
Receiving the incident light, the photodiode (PD) 132 generates the signal charge (photoelectron) (FIG. 10(a)).
Next, when the transfer gate pulse TRANS (high level) is applied to the transfer gate line 155, the signal charge (photoelectron) generated by the photodiode (PD) 132 is transferred to the floating diffusion (FD) 138 (FIG. 10(b)). Here, the level of voltage of the floating diffusion (FD) 138 goes low depending on the transferred signal charge.
Then, when the transfer gate pulse TRANS becomes a low level again, the photodiode (PD) 132 and the floating diffusion (FD) 138 are blocked (FIG. 10(c)).
Since recent miniaturization of solid-state imaging devices formed out of semi-conductor causes a decrease in breakdown voltage, resulting in a lower power supply voltage, the signal charge (photoelectron) received at the floating diffusion (FD) 138; namely an FD capacitance, decreases. The decrease in the FD capacitance lowers the number of saturated electrons in the floating diffusion (FD) 138 and makes detection of high intensity luminance impossible, resulting in a lower dynamic range. The decrease also causes difficulty in transferring to the floating diffusion (FD) 138 the signal charge (photoelectron) generated by the photodiode (PD) 132, leading to producing residual image electrons in the photodiode (PD) 132.
Patent Reference 1 (Japanese Unexamined Patent Application Publication No. 2005-86595) describes a solid-state imaging device having an increased FD capacitance to avoid producing residual image electrons.
The solid-state imaging device in Patent Reference 1 takes advantage of the coupling of parasitic capacitance C102 generated between the column signal line 153 and the floating diffusion (FD) 138 in FIG. 8 to increase a reset level of voltage (FD reset level of voltage) of the floating diffusion (FD) 138 greater than a power supply voltage VDD in order to increase the FD capacitance (hereinafter referred to as a coupling effect of C102). Illustrated next in FIGS. 11A and 11B are timing diagrams of the solid-state imaging device described in Patent Reference 1.
Here, FIG. 11A is a timing diagram showing the operation of the conventional solid-state imaging device in Patent Reference 1 with no electric charge generated by the photodiode (PD) 132.
FIG. 11B is a timing diagram showing the operation of the conventional solid-state imaging device in Patent Reference 1 with an electric charge generated by the photodiode (PD) 132.
Compared with the conventional example 1, the solid-state imaging device in Patent Reference 1 is characterized to have a high level period (t1 to t2b) of the reset signal RST shorter than a rising period (t1 to t2) of a column signal line.
This causes the rise of the column signal line 153 in the t2b to t2 period in FIGS. 11A and 11B to bring the level of voltage of the floating diffusion (FD) 138 high via the parasitic capacitance C102 existing between the column signal line 153 and the floating diffusion (FD) 138 in FIG. 8. Hence, the FD reset level of voltage 2 in FIG. 11B is higher than the potential in the conventional example 1 (FD reset level of voltage 1 in FIG. 9B). This allows the solid-state imaging device described in Patent Reference 1 to store as many signal charges (photoelectrons) as possible in the floating diffusion (FD) 138 in order to prevent residual images.